1. Field of the Invention.
The present invention relates to a semiconductor memory called a stacked CMOS SRAM in which a load transistor of a flip-flop constituting a memory cell is formed of a semiconductor layer on a semiconductor substrate.
2. Description of the Prior Art
In a resistance load MOS SRAM generally used as a conventional MOS SRAM, it has become difficult to maintain a high memory retention capacity level while a standby current is kept low.
In order to provide a countermeasure against the above drawback, a full CMOS SRAM having a memory cell shown in FIG. 1 is proposed. And further, in order to reduce a chip area of the full CMOS SRAM to that of a resistance load MOS SRAM, there is proposed a so-called stacked CMOS SRAM wherein load PMOS transistors 12 and 13 of a flip-flop 11 constituting a memory cell are formed by thin film transistors, and these thin film transistors are stacked on driver NMOS transistors 14 and 15 and transfer NMOS transistors 16 and 17 formed by bulk transistors (e.g., "Nikkei Microdevice" (September, 1988), pp. 123-130).
FIG. 2 shows an example of such a stacked CMOS SRAM. In this SRAM, impurity diffused regions 21a to 21g serving as source/drain regions of the driver NMOS transistors 14 and 15 and transfer NMOS transistors 16 and 17 are formed in a semiconductor substrate.
Gate electrodes 14a to 17a of the transistors 14 to 17 are formed by a first poly-Si layer on an insulating film (not shown) on the semiconductor substrate. Note that the gate electrodes 16a and 17a are parts of a word line 22.
The gate electrode 14a is connected to the impurity diffused region 21d, and the gate electrode 15a is connected to the impurity diffused regions 21b and 21f.
The gate electrodes 14a and 15a, the word line 22 and a surface of the semiconductor substrate are covered with an insulating interlayer (not shown). The gate electrodes 12a and 13a of the PMOS transistors 12 and 13 are formed by a second poly-Si layer on this insulating interlayer.
As described above, the gate electrodes 12a and 13a are made of a poly-Si layer different from that of the gate electrodes 14a and 15a and can have a length different from that of the gate electrodes 14a and 15a, as is apparent from FIG. 2.
Gate electrodes 12a and 13a are respectively connected to the gate electrodes 14a and 15a through contact holes 23 and 24 formed in the underlying insulating interlayer.
The gate electrodes 12a and 13a and the like are covered with a gate insulating film (not shown). On this gate insulating film, a power source line 25 and active layers 26 and 27 of the PMOS transistors 12 and 13 which are connected to this power source line 25 are made of a third poly-Si layer.
Drain regions of the active layers 26 and 27 are respectively connected to the gate electrodes 15a and 12a through contact holes 31 and 32 formed in the underlying insulating film.
The power source line 25, the active layers 26 and 27 and the like are covered with an insulating interlayer (not shown), and a ground line 33 made of a first Al layer is formed on this insulating interlayer.
The ground line 33 is connected to the impurity diffused region 21c and the like through a contact hole 34 and the like formed in the underlying insulating film.
The ground line 33 and the like are covered with an insulating interlayer (not shown). Bit lines 35 and 36 are made of a second Al layer on this insulating interlayer.
The bit lines 35 and 36 are respectively connected to the impurity diffused regions 21g and 21e through contact holes 37 and 38 formed in the underlying insulating film.
The impurity diffused regions 21g and 21e and the contact holes 37 and 38 are shared by two adjacent memory cells formed in a direction perpendicular to the word line 22 and are formed on the boundary line of these memory cells.
As is apparent from the above description, in the stacked CMOS SRAM, it is most effective to form the active layers 26 and 27 of the PMOS transistors 12 and 13 and the power source line 25 by a single poly-Si layer when the fabrication process is taken into consideration.
In order to form the active layers 26 and 27 and the power source line 25 by a single poly-Si layer, gaps S exceeding at least the limit of the lithographic process must be assured between the active layers 26 and 27 and the power source line 25.
In order to assure the layout of the active layers 26 and 27 and the power source line 25, the memory cell area must also be assured. Therefore, it is not easy to increase the packing density of the conventional example shown in FIG. 2.
On the other hand, in such a stacked CMOS SRAM, it is very important to reduce OFF leakage currents of the PMOS transistors 12 and 13 in order to decrease current consumption and improve data retention characteristics. As a method of realizing this, a method of forming a thin poly-Si layer to constitute the active layers 26 and 27 of the PMOS transistors 12 and 13 is considered to be most promising.
In the stacked CMOS SRAM, the power source line 25 is generally formed by the same poly-Si layer as that constituting the active layers 26 and 27 of the PMOS transistors 12 and 13.
When a thin poly-Si layer is formed as described above, an electric resistance of the power source line 25 is increased, and a high-speed operation and operational stability of the memory cells are disadvantageously degraded.
On the other hand, in order to solve the above problem, when an additional conductive layer is formed to reduce the resistance of the power source line 25, the memory cell area is increased, and the fabrication process is complicated.